This invention relates generally to a programmable logic circuit and, more particularly, to a programmable array logic (PAL) circuit which incorporates a J-K register on each output.
U.S. Pat. No. 4,124,899 to Birkner, et al shows a programmable logic circuit which is referred to as a programmable array logic, or PAL, circuit. A PAL comprises a programmable array or matrix interconnecting a plurality of circuit inputs and the inputs to a plurality of AND gates. The outputs of the AND gates, which logically are products of selected polarities of selected inputs, are subgrouped and are nonprogrammably connected as inputs to individual, specified OR gates. The outputs of the OR gates are, logically speaking, sums of these product terms.
One architectural feature shown in U.S. Pat. No. 4,124,899 is the use of D type registers or flip-flops with each of the circuit outputs. The D registers are provided at the OR gate outputs and allow temporary storage of the sum of the product term produced. Additionally, a feedback path from the output of each register to the array may be provided. This arrangement forms a state sequencer which can be programmed to execute elementary sequences, such as count up, count down, shift, skip and branch.
Like the device shown in U.S. Pat. No. 4,124,899, other synchronous PAL's on the market today typically include D type edge-triggered registers. However, for sequential circuit design, a J-K register is a more flexible and advantageous component. Unfortunately, incorporation of a J-K register into the standard PAL circuit architecture would require either the addition of more product terms (PT's) for connection to the K input of the J-K register or, alternatively, division of the current allotment of PT's between the J and K inputs. The former approach increases the size and power consumption of the device and is, therefore, unattractive. The latter approach reduces the number of PT's per output available to the designer and, thus, is also unattractive.
An object of the present invention is to provide a PAL circuit architecture which incorporates J-K registers for sequential system design.
Another object of the present invention is to provide a PAL circuit architecture which incorporates J-K registers without requiring the addition of additional product terms for the K input of the register.
Yet another object of the present invention is to provide a PAL circuit architecture which incorporates J-K registers without requiring a reduction in the allocation of product terms per output for the J and K register inputs.
These objects are attained in a programmable logic circuit which includes an array having a plurality of inputs for receiving input terms and a plurality of outputs and circuitry for combining selected ones of the input terms to form product terms at each of the array outputs. A J-K register having a first output connected to the output of the logic circuit, and circuitry for selectively connecting each of the array outputs to either or both of the J and K inputs of the J-K register, are also included. In a preferred embodiment, the second (inverted) output of the J-K register is connected in a feedback arrangement as an input to the array.
The circuitry for selectively connecting each of the array outputs to the J and K register inputs comprises a programmable element serially connected to circuitry for electrically isolating the J and K inputs. In a preferred embodiment, the isolating circuitry includes a three-terminal device having a first terminal connected to the respective J or K input via a programmable element, a second terminal connected to a power source and a third terminal connected to the array output. In this preferred embodiment, the three-terminal device is a transistor having a control terminal (i.e., the third terminal) connected to the array output.
The J-K register may be selectively converted to a D register or a toggle register by on-chip programmable circuitry. For operation as a toggle register, the array is programmed to present identical sums-of-the-product terms to both J and K inputs of a given register. For operation as a D register, the array is similarly programmed, but the output connected to the K input is selectively inverted by an on-chip programmable inverter.
The PAL architecture of the present invention increases the effective number of PT's without increasing the actual total number. The isolation circuitry associated with each of the logic circuit outputs allows both J and K inputs of the register to share each of the product terms. Thus, the new PAL architecture increases the effective number of PT's and allows for incorporation of J-K registers without increasing device power consumption, degrading device speed, or reducing the allotment of PT's per output.
It should be noted that the programmable logic circuit of the present invention is intended to include devices which are mask programmable, as well as field programmable. In devices of the latter type, the programming feature of the present invention allows the user to recover from programming errors and make design changes without necessarily having to sacrifice the device. However, for particular high volume applications, a mask programmable device which incorporates J-K registers according to the present invention may be cost effective.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.